1. Field of the Invention
The present invention relates to the design automation of logic devices, and more particularly to techniques for a logic change process in the design automation.
2. Description of the Related Art
In general, in the automatic design of a logic device, gate logic descriptions which define the logic device in terms of expressions of lower abstraction are automatically synthesized from function logic descriptions which define the logic device in terms of expressions of higher abstraction.
In such an automatic logic device design, a design change at the level of function logic is sometimes made after the origination of the gate logic descriptions has been followed by the addition of information (for example, cell placement information for an LSI) as required for the design. In such a case, the automatic logic synthesis process needs to be executed again so as to reflect the design change at the function logic level on the gate logic descriptions.
A technique for the automatic logic synthesis at the occurrence of the design change as stated above, has been known from the official gazette of Japanese Patent Application Laid-open No. 72070/1987.
According to this technique, steps for finding out which parts of the logic have changed at the level of gate logic are comprised, and only the changed part is renewed, whereby the design change can be reflected on the gate logic level without losing the additional information of the other part at the gate logic level.
With the prior-art method, however, the logic changed part of the logic is found out in such a way that the gate logic description being a lower-rank or minor description is once synthesized from the function logic description being a higher-rank or major description, and that the description synthesized anew is compared with the current gate logic descriptions over the whole of logic device. Therefore, the method has had the problem that a very long time is expended on the logic change process in the application thereof to large scale object to be-designed.
In addition, as work stations have had their performances enhanced and have come into wide use, a computer environment for aid in the logic design has been turned into a distributed processing system configured of a plurality of processors. Therefore, the prior-art technique has posed the problem that the amount of information items which are transmitted among the processors becomes enormous.